L5980 0.7A Buck Switching Regulator


0.7A DC output current

2.9 V to 18 V input voltage

Output Voltage Adjustable from 0.6 V

250 kHz switching frequency, programmable up to 1 MHz

Internal soft-start and inhibit

Low dropout operation: 100% duty cycle

voltage feedforward

No-load current operation

Overcurrent and Thermal Protection

VFQFPN8 3 x 3 mm package


Consumer: Set-top boxes, DVDs, DVD recorders, car audio, LCD TVs and monitors

Industrial: Chargers, PLDs, PLAs, FPGAs

Networking: XDSL, modem, DC-DC module

Computer: CD storage, hard disk, printer, sound card/graphics card

LED driver


The L5980 is a buck switching regulator with the smallest embedded power AMOSFET, so it is capable of delivering more than 0.7A of DC current to the load depending on application conditions. Input voltages range from 2.9 volts to 18 volts, while output voltages can range from 0.6 V to VIN. With a minimum input voltage of 2.9V, the unit also works with a 3.3V bus. Requiring minimal external components, the unit includes an internal 250 kHz switching external frequency oscillator tuned to 1 MHz. The FVQFPN package with exposed pad allows reduction to about 60°C/W.

Electrical Characteristics

1. Over the temperature range of -40 to +125°C, refer to TJ's specification. Specifications over a temperature range of -40 to +125°C are guaranteed by design, characterization and statistical correlation.

2. Design guarantee.

Function description

The L5980 is based on "Constant Frequency Control Mode". The output voltage VOUT is supplied by the feedback pin (FB) and provides an error signal compared to a fixed frequency sawtooth wave, which controls the power switch. The main internal modules are shown in the block diagram in Figure 3. They are: a fully integrated oscillator that provides a sawtooth wave to adjust the duty cycle and sync signal. Its switching frequency can be adjusted by external and external resistors. The voltage and frequency feedforward is realized. z Soft-start circuit to limit the inrush current during the start-up phase. Voltage Mode Error Amplifier Pulse Width Modulator and associated logic circuitry required to drive the internal circuitry power switches. High-side drive for embedded p-channel power MOSFET switches. z Peak current limit sensing block for handling overload and short circuit conditions. z A regulator and internal reference. It provides internal circuitry and provides a fixed internal reference. A voltage monitoring circuit (UVLO) that checks the input and internal voltages. Thermal shutdown block to prevent thermal runaway.

Oscillator and Sync

Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides a constant frequency clock. Its frequency depends on the resistor pin externally connected to the FSW. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as shown in Figure 6 with an external resistor to ground. To improve the line transient performance and keep the PWM gain at a constant voltage with the input, voltage feedforward is achieved by changing the slope of the sawtooth according to the change in input voltage (see Figure 5.a). If the oscillator frequency is increased by an external resistor. This achieves frequency feedforward (Fig. 5.b) to keep the PWM gain constant with the switching frequency (see the expression for PWM gain in Section 5.4). A sync signal is generated on the sync pin. The phase shift of this signal is 180° from the clock. This delay is useful when two devices are synchronizing to connect the sync pins together. When the sync pins are connected, the device's higher oscillator frequency acts as the master, so the slave switches in frequency but with a half-cycle delay. This minimizes the rms value of the current through the input capacitor [see L5988D datasheet].

The unit can work synchronously, feeding an external clock signal at a higher frequency. Synchronously changing the sawtooth amplitude, changing the PWM gain (Fig. 5.c). This change must be taken into account when studying loop stability. To minimize the change in PWM gain, the free-running frequency (using the resistor on the FSW pin) should be set only slightly below the external clock frequency. A change in this pre-adjusted frequency changes the sawtooth slope for negligible truncated sawtooth, due to external synchronization.

soft start

Soft start is the key to ensure the correct and safe start of the buck converter. It avoids the impact of inrush current and makes the output voltage rise once. Soft start is an amplifier performed by a step ramp on the wrong non-inverting input (VREF). So the output voltage conversion ratio is:

where SRVREF is the slew rate of the non-inverting input, and R1 and R2 are the resistive divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64 steps from 0 V to 0.6 V, 9.5 mV each. The time base for a step is 32 clock cycles. So the soft-start time and output voltage slew rate depend on the switching frequency

For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms.

Error Amplification and Compensation

An error amplifier (E/A) performs pulse width modulation on the error signal compared to the sawtooth wave. Its non-inverting input is internally connected to a 0.6V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this setup, the error amplifier is a voltage mode operational amplifier with high DC gain and low output impedance. The uncompensated error amplifier characteristics are as follows:

In continuous conduction mode (CCM), the transfer function of the power section has two poles created by the LC filter and zero created by the ESR of the output capacitor. Various compensation network capacitors can be used depending on the ESR value of the output. A Type II compensation network can be used if the zero introduced by the output capacitor helps to compensate for the double poles of the LC filter. Otherwise, the type must use a compensation network (for compensation network selection). Anyway, the way to compensate for the loop is to introduce zeros to get a safe phase margin.

overcurrent protection

The L5980 implements overcurrent protection sensing flowing through the power MOSFET. Current sensing is disabled during the initial stages of conduction time due to noise generated by the switching activity of the power MOSFET. This avoids false detection of fault conditions. This interval is often referred to as "masking time" or "blank time". The masking time is about 200ns. When overcurrent is detected, according to operating conditions.

1. Output voltage regulation. When overcurrent is detected, the power MOSFET is turned off and the internal reference (VREF), which will set the error amplifier to zero and remain in this state for the soft-start time (TSS, 2048 clock cycles). After this time, a new soft-start phase occurs and the internal references start to ramp (see Figure 8.a).

2. Soft start stage. If the overcurrent limit is reached, the power MOSFET turns off for pulse-by-pulse overcurrent protection. During the soft-start phase, during overcurrent conditions, the device can skip pulses to keep the output current constant equal to the current limit. If at the end of the "masking time" when the current is above the overcurrent threshold, the power MOSFET is turned off skipping a pulse. If, at the end of the next "masking time", the current is still above the threshold, the device will skip two pulses. This mechanism is repetitive and the device can skip up to 7 pulses. If at the end of the "blanking time", the number of skipped cycles the current is below the overcurrent threshold is reduced by one unit. At the end of the soft-start phase, the output voltage is in regulation, and if the overcurrent persists, the behavior described above occurs. (See Figure 8.b) Therefore, the overcurrent protection can be summarized as in the soft-start phase, the output is in regulation and the current is constant. If the output is shorted to ground when the output voltage is regulated, the overcurrent triggers the device to cycle 2048 clock cycles starting between "hiccup" (power, MOSFET off, no current to the load) and "constant current", with very short The on-time and switching frequency are reduced (up to one-eighth of the normal switching frequency). See Figure 30. short-circuit behavior.

Inhibit function

The blocking function allows the device to be turned off. With INH pin above 1.9 V the device is disabled, power consumption is reduced to below 30µA pin below 0.6 V, the device is enabled. If the INH pin is left floating, an internal pull-up ensures that the voltage on the pin reaches the inhibit threshold and the device is disabled. This pin is also compatible with VCC.

Hysteretic thermal shutdown

The thermal shutdown module generates a signal that shuts down the power stage where the temperature exceeds 150°C. Once the junction temperature returns to around 130°C, the device restarts during normal operation. The sensing element is very close to the PDMOS thus ensuring accurate and fast temperature detection.

Application Information

Input Capacitor Selection

Capacitors connected to the input must be able to support the operating voltage and maximum rms input current required by the largest input device. The input capacitor is subject to pulsed current, whose rms value dissipates across its ESR, affecting the efficiency of the overall system. So the current rating of the input capacitor must be higher than the maximum rms input current and ESR value to match the expected efficiency. The maximum rms input current flowing through the capacitor can be calculated as:


In the formula, Io is the maximum DC output current, D is the duty cycle, and η is the efficiency. Considering η=1, the function has a maximum value at D=0.5, which is equal to Io/2. In a particular application, the range of possible duty cycles must be considered in order to find the maximum rms input current. The maximum and minimum duty cycle can be calculated as:

where VF is the forward voltage across the freewheeling diode and VSW is the voltage drop across the internal PDMOS. in Table 6. Multilayer Ceramic Capacitors report suitable for this device

Sensor selection

The inductance value fixes the current ripple through the output capacitor. So the minimum inductance value must be chosen to obtain the expected current ripple. The rule for fixing the current ripple value is to keep the ripple at 20%-40% of the output current. The inductance value can be calculated as follows:

In the formula, TON is the turn-on time of the internal high-side switch, and TOFF is the turn-on time of the external diode (in CCM, FSW=1/(TON+TOFF)). Maximum current ripple, obtained at fixed Vout at maximum TOFF (minimum duty cycle) (see previous section to calculate minimum duty). Therefore, taking ΔIL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated as:

Where FSW is the switching frequency, 1/(TON+TOFF).

For example, VOUT=3.3 V, VIN=12 V, IO=0.7 A, FSW=250 kHz, the minimum value of ΔIL=30% IO is about 45μH. The peak current is given by the inductor:

Therefore, if the inductor value decreases, the peak current (which must be below the current device limit) increases. The higher the inductance value, the higher the average current that can be sourced without hitting the current limit. The table below lists some inductor part numbers.

Capacitor output selection

The current in the capacitor has a triangular waveform, creating a voltage ripple across it. This ripple is caused by capacitive elements (charging and discharging of the output capacitor) and resistive elements (due to the voltage drop across the ESR). Therefore, the output capacitor must be selected to match the voltage ripple to the application requirements. The amount of voltage ripple can be calculated from the current ripple obtained and selected by the inductor.

If the ripple of the resistive element is usually much higher than the capacitive element, the output capacitor used is not a multilayer ceramic capacitor (MLCC) value with very low ESR. The output capacitor is also important for loop stability: it fixes the dual LC filter poles and zeros due to its ESR. Chapter 5 will show how to consider its potency system stability. For example, when VOUT=3.3V, VIN=12V, ΔIL=0.21A (generated by the inductor value), in order to make ΔVOUT=0.01·VOUT, if a multilayer capacitor is used, then 10μF can ignore the ESR to the output voltage ripple Impact. If there is no negligible ESR (electrolytic or tantalum capacitors), the selection of capacitors takes into account the calculation of their ESR value. Therefore, at 100µF with ESR = 40mΩ, the voltage drop dominates, and the voltage ripple is 8.4mv. The output capacitor is also important to maintain the output voltage during load transients where a high slew rate is required. The output capacitor supplies current to the load when the load transient slew rate exceeds the system bandwidth. So if high slew rate load transients are required for the application the output capacitance and system bandwidth must be chosen to sustain the load transients. The table below lists some capacitor families.