The OP470 is a very low noise quad operational amplifier


• Very low noise, 5 nV/[email protected] kHz

• Good input bias voltage, 0.4mV max

• Low offset voltage drift, 2 μV/°C max

• Very high gain, min. 1000 V/mV

• Excellent CMR, 110 dB minimum

• Slew rate, 2V/μs typical

• Gain-bandwidth product, 6 MHz typical

• Industry standard four-pin

• Supplied in mold form

General Instructions

The OP470 is a high performance monolithic quad operational amplifier with extremely low voltage noise, 5nV/Hz, 1kHz maximum, and performance comparable to ADI's industry standard OP27.

The OP470 features an input offset voltage of less than 0.4 mV, ideal for quad op amps, and an offset drift of less than 2 mV/∞C, guaranteed over the full military temperature range. The open loop gain of the OP470 exceeds 1,000,000 at 10 kW load, ensuring excellent gain accuracy and linearity even in high gain applications. The input bias current is less than 25na, reducing the error caused by the signal source resistance. The OP470's CMR exceeds 110dB and PSRR is less than 1.8mV/V, significantly reducing errors caused by ground noise and power supply fluctuations. A quad OP470 consumes half the power of four OP27s, a significant advantage for power-conscious applications. The OP470 is unity gain stable with a gain bandwidth product of 6mhz and a slew rate of 2v/ms.

The OP470 provides excellent amplifier matching, which is important for applications such as multiple gain blocks, low noise instrumentation amplifiers, quad buffers and low noise active filters.

The OP470 meets industry standard 14 lead dipped pins. It is pin compatible with the LM148/149, HA4741, HA5104 and RM4156 quad op amps and can be used to upgrade systems using these devices.

For higher speed applications, the OP470 with a slew rate of 8V/ms is recommended.

pin connection

Simplified schematic

Dice Features

OP470 – Typical Performance Characteristics

application information

Voltage and Current Noise

The OP470 is a very low noise quad op amp with typical voltage noise of only 3.2 nV÷Hz at 1 kHz. Since voltage noise is inversely proportional to the square root of the collector current, the very low noise characteristics of the OP470 are achieved in part by operating the input transistors at high collector currents. However, current noise is proportional to the square root of the collector current. Therefore, the excellent voltage noise performance of the OP470 comes at the expense of current noise performance, which is typical of low noise amplifiers.

To obtain the best noise performance in a circuit, it is necessary to understand the relationship between voltage noise (en), current noise (in), and resistance noise (et).

Total Noise and Source Resistance

The total noise of the op amp can be calculated by the following formula:


En = total input referred noise

en = voltage noise on amps

in = op amp current noise

et = source resistance thermal noise

RS = source resistance

The total noise refers to the input, and the noise at the output will be amplified by the circuit gain. Figure 4 shows the relationship between total noise and source resistance at 1kHz. For RS < 1 kW, the total noise is dominated by the voltage noise of the OP470. When RS rises above 1KW, the total noise increases, dominated by the resistor noise rather than the OP470 voltage or current noise. When the RS exceeds 20kw, the current noise of the OP470 becomes the main contributor to the total noise.

Figure 5 also shows the relationship between total noise and source resistance, but at 10 Hz. Since the current noise is inversely proportional to the square root of frequency, the total noise is faster than that shown in Figure 4. In Figure 5, when RS>5kw, the current noise of OP470 dominates the total noise.

As can be seen from Figure 4 and Figure 5, to reduce overall noise, the source resistance must be kept to a minimum. In applications with high source resistance, the OP400 with lower current noise will provide lower overall noise compared to the OP470.

Figure 6 shows the peak-to-peak noise versus source resistance in the 0.1Hz to 10Hz range. Likewise, at low RS values, the OP470 voltage noise is the dominant contributor to peak-to-peak noise, while current noise is the dominant contributor when RS is increased. The intersection of peak-to-peak noise between OP470 and OP400 is RS=17 kW.

The OP471 is a higher speed version of the OP470 with a slew rate of 8V/ms. The OP470 is only slightly more noisy than the OP470. Like the OP470, the OP471 is unity-gain stable.

Table 1 lists the typical source resistance of some signal sources for reference.

Noise measurement - peak-to-peak voltage noise

The circuit in Figure 7 is a test setup for measuring peak-to-peak voltage noise. To measure the OP470 200 nV peak-to-peak noise specification from 0.1 Hz to 10 Hz, the following precautions must be observed:

1. The device must be warmed up for at least five minutes. As shown in the warm-up drift curve, the offset voltage typically changes by 5 mV after power-up due to the increase in die temperature. These temperature-induced effects can exceed tens of millivolts within a 10-second measurement interval.

2. For similar reasons, equipment must be well shielded from airflow. Shielding also minimizes the effects of thermocouples.

3. Sudden motion near the device can also "feedthrough" to increase the noise observed.

4. The test time for measuring 0.1 Hz to 10 Hz noise shall not exceed 10 seconds. As shown in the noise tester frequency response curve in Figure 8, the 0.1 Hz corner is defined by only one pole. A test time of 10 seconds was used as an additional pole to remove noise contributions in the frequency band below 0.1 Hz.

5. When measuring noise on a large number of devices, a noise voltage density test is recommended. The 10 Hz noise voltage density measurement correlates well with the 0.1 Hz to 10 Hz peak-to-peak noise reading, as both results are determined by the location of the white noise and the 1/f corner frequency.

6. The test circuit should be powered from a well-bypassed, low-noise power source such as a battery. This will minimize output noise introduced through the amplifier supply pins.

Noise Measurement - Noise Voltage Density

The circuit of Figure 9 shows a fast and reliable method for measuring the noise voltage density of a quad op amp. Each individual amplifier is connected in series and is at unity gain, saving the final amplifier is at non-reciprocal gain of 101. Since the AC noise voltages of each amplifier are uncorrelated, they increase in a rms fashion, resulting in:

The OP470 is a monolithic device with four identical amplifiers.

The noise voltage density of each individual amplifier will match, giving:

Noise Measurement - Current Noise Density

The test circuit shown in Figure 10 can be used to measure the current noise density. The relationship between voltage output and current noise density is:


G = get 10000

RS=100 kW source resistance

Capacitive Load Drive and Power Supply Considerations

The OP470 is unity gain stable and capable of driving large capacitive loads without oscillation. Still, bypassing the good supply is highly recommended. Proper power supply bypassing can reduce problems caused by power line noise and improve the OP470 capacitive load drive capability.

In a standard feedback amplifier, the output resistance of the op amp combines with the load capacitance to form a low-pass filter that adds phase shift and reduces stability in the feedback network. Figure 11 shows a simple circuit that eliminates this effect. The added components C1 and R3 decouple the amplifier from the load capacitance and provide additional stability. The C1 and R3 values shown in Figure 11 are for load capacitances up to 1000pF when used with the OP470.

In applications where the inverting or non-inverting input of the OP470 is driven by low source impedance (below 100 W) or grounded, excessive parasitic currents can result if V+ is applied before V-, or when V is disconnected. Most applications use dual trace power supplies and the device power pins are properly bypassed and power up should not be a problem. If V- is disconnected, a source resistance of at least 100 W in series with all inputs (Figure 11) will limit parasitic currents to safe levels. It should be noted that any source resistance, even 100 watts, will add noise to the circuit. Where noise requirements are kept to a minimum, germanium or Schottky diodes can be used to clamp the V-pin and eliminate parasitic currents instead of using series limiting resistors. For most applications, only one diode clamp is required per board or system.

Unity Gain Buffer Applications

When Rf is 100 W and the input is driven by fast, large signal pulses (>1 V), the output waveform is shown in Figure 12.

In the fast feedthrough-like portion of the output, the input protection diode effectively shorts the output to the input, and the signal generator will produce a current limited only by the output short-circuit protection. At 500 watts RF, the output can handle the current requirements (IL < 20 mA at 10 volts); the amplifier will remain in its active mode and a smooth transition will occur.

When Rf > 3kw, the pole formed by Rf and the amplifier's input capacitance (2pf) creates additional phase shift and reduces the phase margin. A small capacitor (20 pF to 50 pF) in parallel with the RF helps eliminate this problem.


low noise amplifier

Figure 13 shows a simple way to reduce amplifier noise by paralleling amplifiers. Amplifier noise, as shown in Figure 14, is about 2 nV/[email protected] kHz (R.T.I.). The gain of each paralleled amplifier and the entire circuit is 1000. The 200 watt resistors limit the circulating current and provide an effective output resistance of 50 watts. The amplifier is stable under a capacitive load of 10mA and can provide up to 30mA of output drive.

Digital Pan Control

Figure 15 uses a DAC-8408 four-bit 8-bit DAC to shift the signal between two channels. The complementary DAC current outputs two of the four DACs of the DAC-8408, driving a current-to-voltage converter consisting of a single four OP470. The amplifier has complementary outputs whose amplitude depends on the digital code applied to the DAC. Figure 16 shows the complementary output of a 1kHz input signal and digital ramp applied to the DAC data input. The distortion of digital panning control is less than 0.01%.

Gain errors due to mismatches between the internal DAC ladder resistors and the current-voltage feedback resistors are eliminated by using the feedback resistors inside the DAC. Of the four DACs available in the DAC-8408, only two (A and C) actually pass the signal. DACs B and D are used to provide the additional feedback resistors required in the circuit. Current-to-voltage converters using RFBB and RFBD are not affected by the digital data reaching DACs B and D if the VREFB and VREFD inputs are left unconnected.

Squelch Amplifier

The circuit of Figure 17 is a simple squelch amplifier that uses a FET switch to cut off the output when the input signal falls below a preset limit.

The input signal is sampled by a peak detector and the time constant is set by C1 and R6. When the output of the peak detector (Vp) is lower than the threshold voltage (VTH) set by R8, the comparator formed by the operational amplifier C switches from V- to V+. This turns the gate that drives the N-channel FET high, turning it on and reducing the gain of the inverting amplifier formed by op-amp A to zero.


Five-band low-noise stereo graphic equalizer

The graphic equalizer circuit shown in Figure 18 provides 15 dB of boost or cut over a 5-band range. For a 3V rms input, the signal-to-noise ratio is better than 100dB over a 20kHz bandwidth. Larger inductors can be replaced with active inductors, but this will reduce the signal-to-noise ratio.